1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to the formation of dummy structures within a semiconductor topography.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Substantially planar surfaces within a semiconductor topography may play an important role in fabricating overlying layers and structures. For example, step coverage problems may arise when a material is deposited over a surface having raised and recessed regions. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Furthermore, correctly patterning layers upon a surface containing fluctuations in elevation may be difficult using optical lithography. The depth-of-focus of the lithography alignment system may vary depending upon whether the resist resides in an elevational xe2x80x9chillxe2x80x9d or xe2x80x9cvalleyxe2x80x9d area. Furthermore, substantially planar surfaces may become increasingly important as the feature sizes of semiconductor devices are reduced, since the depth of focus required to pattern an upper surface of a topography may increase with reductions in feature size. If a topography is nonplanar, the patterned image may be distorted and the intended structure may not be formed to the specifications of the device.
A technique that is often used to planarize or remove the elevational fluctuations in the surface of a semiconductor topography is chemical mechanical polishing xe2x80x9cCMP.xe2x80x9d A conventional CMP process may involve placing a semiconductor wafer face-down on a polishing pad which lies on or is attached to a table or platen. During the CMP process, the polishing pad and/or the semiconductor wafer may be set into motion as the wafer is forced against the pad. An abrasive, fluid-based chemical suspension, often referred to as a xe2x80x9cslurry,xe2x80x9d may be deposited onto the surface of the polishing pad. The slurry fills the space between the polishing pad and the wafer surface such that a chemical in the slurry may react with the surface material being polished. The rotational movement of the polishing pad relative to the wafer causes abrasive particles entrained within the slurry to physically strip the reacted surface material from the wafer. Therefore, the CMP process may employ a combination of chemical stripping and mechanical polishing to form a planarized surface.
Unfortunately, a CMP process may not form a substantially planar surface across an entire semiconductor topography. For instance, the slurry may react in recessed regions, causing those regions to be excessively etched. Furthermore, the polishing rate of the CMP may be dependent upon the polish characteristics of the topography. In addition, the polishing pad, being somewhat conformal to the surface topography, may deform in response to polishing laterally adjacent layers comprising different polish properties. Therefore, while the removal rate of raised regions of the dielectric may be greater than that of the recessed regions in a typical CMP process, a significant amount of the recessed regions may, unfortunately, undergo removal. This phenomena is known as the xe2x80x9cdishingxe2x80x9d effect and may reduce the degree of planarization that can be achieved by the CMP process. In particular, the dishing effect may cause upper surfaces of layers and structures to curve below polished upper surfaces of adjacent structures or layers. For example, the dishing effect resulting from the fabrication of shallow trench isolation regions may be so severe that portions of the isolation regions may extend below the upper surface of the substrate. Consequently, the active regions of the device may not be adequately isolated.
In general, a topography having relatively wide regions of material may be more prone to the dishing effect than a topography having relatively narrow regions of material. As such, in an effort to reduce the dishing effect in topographies which have relatively wide regions of material, dummy structures are sometimes formed within the topography. In particular, structures which do not affect the functionality of a chip fabricated from the topography may be formed within the topography such that a substantially surface may be obtained. As a result, elevational fluctuations of the topography may be reduced and/or prevented. In general, dummy structures may be fabricated in a square pattern to simplify the layout design within an inactive region. In a preferred embodiment, the dummy structures may be arranged such that a particular plane of a topography has a substantially equal pattern density of components. In this manner, a substantially planar surface across the active and inactive regions of the topography may be obtained during a subsequent polishing process. In general, an active region of a topography may refer to the region of a topography designated for the formation of devices which are adapted to affect the functionality of a chip fabricated from the semiconductor topography. In contrast, an inactive region may refer to a region of the topography, such as an isolation structure, which does not include any devices which affect the functionality of a chip fabricated from the semiconductor topography.
In general, the number of structures that may be formed upon a topography, including those within the active and inactive regions of the topography, is typically limited by the memory space of the CAD system used to layout the chip and the computing power constraints of the system used to simulate the performance of such a chip layout. As such, in order to form active devices within the design specifications of a chip, the number of dummy structures fabricated within a topography is often limited. Such a limitation of the number of dummy structures typically results in fabricating structures with large dimensions relative to the critical dimensions of the devices within the active region of the topography. For instance, in many cases, dummy structures are fabricated with a square pattern of 7.2 xcexcmxc3x977.2 xcexcm, while devices within active regions include sub-micron dimensions. Such large dummy structures, however, may still be susceptible to the dishing effect, resulting in the formation of a non-planar surface subsequent to a polishing process. In some cases, structures and layers formed above such a non-planar surface may not be formed within design specifications of the chip, causing the chip to malfunction or rendered inoperable. As a result, the reliability and production yield of devices fabricated from such a process may be undesirably low. Such a problem may become even more significant as dimensions of active devices within a topography continue to decrease with the advancement of integrated circuit technology.
As such, it would be advantageous to develop a dummy structure layout which allows a substantially planar surface to be formed across a die and/or wafer having active devices with sub-micron critical dimensions. More specifically, it would be beneficial to develop a dummy structure layout which allows a topography to have regions with substantially similar dimensions and pattern densities across the entirety of the topography without exceeding the memory space and computing power constraints of the systems used to layout the chip design and simulate the performance of the chip, respectively.
The problems outlined above may be in large part addressed by a dummy structure layout which includes a pattern of similarly sized and uniformly spaced annular dummy structures for an inactive region of a semiconductor topography. In some cases, such a dummy structure layout may be used to outline a pattern of isolation structures subsequently formed within a semiconductor substrate of the inactive region. More specifically, the dummy structure layout may be used to form isolation structures spaced from each other within the inactive region of the semiconductor topography. In this manner, the pattern density of the semiconductor topography may become more evenly balanced relative to a topography in which a single isolation structure is formed within the entirety of the inactive region. In some cases, the pattern density of a semiconductor topography within a plane extending between the semiconductor substrate and a first interconnect line of a semiconductor topography may be substantially equal due to the use of the dummy structure layout described herein. In general, the active region of the semiconductor topography may refer to a region designated for the formation of features which are adapted to affect the functionality of a chip fabricated from the semiconductor topography. In contrast, an inactive region of the semiconductor topography may refer to a region which does not include any features which affect the functionality of a chip fabricated from the semiconductor topography.
A semiconductor topography is provided herein which includes a contiguous isolation structure configured in a grid pattern within a portion of a semiconductor substrate of the semiconductor topography and a separate isolation structure arranged within a spacing of the grid pattern within the semiconductor substrate. In general, the spacing between the contiguous isolation structure and the separate isolation structure may be less than approximately 1.0 micron. In some embodiments, the spacing between the contiguous isolation structure and the separate isolation structure may be substantially equal to a minimum critical dimension of features included within an active region of the semiconductor topography. In any case, the separate isolation structure may be one of a plurality of separate isolation structures individually arranged within spacings of the grid pattern within the semiconductor substrate. In addition or alternatively, a thickness variation of the contiguous isolation structure across the semiconductor topography may be less than approximately 10% of an average thickness of the contiguous isolation structure.
In some embodiments, the dummy structures may be removed subsequent to the formation of the isolation structures. In addition, the regions of the semiconductor substrate previously underlying the dummy structures may be introduced with dopants to form diffusion regions interposed between the isolation structures of the inactive region. As such, a semiconductor device is provided which includes an inactive region with a plurality of similarly sized and uniformly arranged annular diffusion regions. In addition, the inactive region may further include isolation structures individually surrounded by the annular diffusion regions. In general, the plurality of annular diffusion regions may include widths of less than approximately 1.0 micron. For example, in some cases, the plurality of annular diffusion regions may include widths substantially equal to a minimum critical dimension of features included within an active region of the semiconductor device.
In any case, the inactive region of the semiconductor topography described herein may include dummy structures other than the ones used to pattern the isolation structures. For example, the inactive region may include a conductive dummy structure arranged above one of the isolation structures of the inactive region. In this manner, the design layout for the inactive region may be adapted such that the conductive dummy structure may be formed upon an isolation structure. In particular, the design layout may be configured such that isolation regions formed within the semiconductor substrate may be large enough to receive subsequently formed dummy structures. Consequently, a semiconductor topography is provided which includes an inactive region with a sacrificial annular dummy structure configured to surround an area exclusively designated for a formation of an isolation structure within the semiconductor substrate of the semiconductor topography. Such an area is preferably larger than a square of a minimum critical dimension of the devices within the active region. In some cases, the conductive dummy structure may be arranged within the same horizontal plane as at least some of the features of the active region. In addition or alternatively, the conductive dummy structure may be one of a plurality of conductive dummy structures individually arranged above the isolation structures of the inactive region.
There may be several advantages to forming semiconductor topographies using the dummy structure layout described herein. For example, the pattern density of components across a semiconductor topography may be substantially equal. Consequently, the xe2x80x9cdishing effectxe2x80x9d of a polishing process may be reduced such that a substantially planar upper surface of a semiconductor topography may be formed. In this manner, overlying structures and layers may be formed within design specifications of a device formed therefrom. More specifically, step coverage problems and lithography problems may be minimized and patterning distorted structures and layers may be avoided. Consequently, production yield of chips fabricated from such topographies may be increased relative to topographies formed from conventional dummy structure layouts. In addition, the dummy structure layout described herein may reduce the amount of memory space used to design a chip layout as well as the computing power constraints of the system used to simulate the performance of such a chip. Furthermore, the time used to fabricate the mask used to form the isolation structures of the semiconductor topography may be reduced, reducing the cost of such a mask.